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refactoring of timing constants

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Hexa Dust
2025-07-18 20:31:23 +01:00
parent 56f2738ea2
commit cba331b939
2 changed files with 17 additions and 14 deletions
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11
src/main.rs
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@@ -44,11 +44,12 @@ pub const DISPLAY_SEGMENTS_EXP: usize = 2;
pub const DISPLAY_SEGMENT_EXP_MINUS: usize = 6; pub const DISPLAY_SEGMENT_EXP_MINUS: usize = 6;
// Timing // Timing
pub const IO_SEG_REFRESH_FREQ: u32 = 1000; // Segment timer freq; from 62 to 15779 for 8bit counter // Note: it takes ~224 μs to read keyboard after segment off
pub const IO_SEG_ON_DIV: u32 = 4; // How long to hold segment LEDs on as part of time for segment timer pub const IO_SEGMENT_RATE_US: u32 = 1000; // Time in μs between segment updates
pub const IO_SEGMENT_ON_US: u32 = 200; // How long in μs to hold segment LEDs on
// Calculator setup
pub const STACK_DEPTH: usize = 7; pub const STACK_DEPTH: usize = 7;
type Calc = StackCalc<f32, STACK_DEPTH, 5, u8>; type Calc = StackCalc<f32, STACK_DEPTH, 5, u8>;
// Interrupt driven I/O // Interrupt driven I/O
@@ -529,8 +530,8 @@ fn main() -> ! {
}); });
timer::segment_timer_init( timer::segment_timer_init(
dp.TC0, // Timer0 (8bit) dp.TC0, // Timer0 (8bit)
IO_SEG_REFRESH_FREQ, // run segments at 100Hz IO_SEGMENT_RATE_US,
IO_SEG_ON_DIV, // 1/10th of 100Hz, 1ms segment on time IO_SEGMENT_ON_US,
); );
unsafe { unsafe {
avr_device::interrupt::enable(); avr_device::interrupt::enable();

18
src/timer.rs
View File

@@ -1,11 +1,13 @@
use arduino_hal::{clock::Clock, pac::TC0, DefaultClock}; use arduino_hal::{clock::Clock, pac::TC0, DefaultClock};
// Raises two interrupts: TIMER0_COMPA every period cycles/1024 // Sets up timer to rise two interrupts:
// and TIMER0_COMPB compb_cocunt cycles/1024 after TIMER0_COMPA // 1. TIMER0_COMPA - every segment_rate_us μs
pub fn segment_timer_init(tc0: TC0, seg_freq: u32, on_div: u32) { // 2. TIMER0_COMPB - segment_on_us μs after TIMER0_COMPA
// 16_000_000 / 1024 / 100 => 156 (100Hz|10ms) pub fn segment_timer_init(tc0: TC0, segment_rate_us: u32, segment_on_us: u32) {
let ocra = DefaultClock::FREQ / 1024 / seg_freq; // 16_000_000 / 64 * 1000 / 1_000_000 => 250
let ocrb: u32 = ocra / on_div; let ocra = DefaultClock::FREQ / 64 * segment_rate_us / 1_000_000;
let ocrb = DefaultClock::FREQ / 64 * segment_on_us / 1_000_000;
assert!(ocra > ocrb);
// Use CTC mode: reset counter when matches compare value // Use CTC mode: reset counter when matches compare value
tc0.tccr0a.write(|w| w.wgm0().ctc()); tc0.tccr0a.write(|w| w.wgm0().ctc());
@@ -16,8 +18,8 @@ pub fn segment_timer_init(tc0: TC0, seg_freq: u32, on_div: u32) {
tc0.ocr0b tc0.ocr0b
.write(|w| w.bits(ocrb.try_into().expect("timer init on_div out of rage"))); .write(|w| w.bits(ocrb.try_into().expect("timer init on_div out of rage")));
// Slow down the timer (CLK / prescale) // Slow down the timer (CLK / prescale)
tc0.tccr0b.write(|w| w.cs0().prescale_1024()); tc0.tccr0b.write(|w| w.cs0().prescale_64());
// Raise interrupt on counter TOP (reset) // Raise interrupt on TOP (reset)
// Raise interrupt on B match // Raise interrupt on B match
tc0.timsk0 tc0.timsk0
.write(|w| w.ocie0a().set_bit().ocie0b().set_bit()); .write(|w| w.ocie0a().set_bit().ocie0b().set_bit());