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refactoring of timing constants

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Hexa Dust
2025-07-18 20:31:23 +01:00
parent 56f2738ea2
commit cba331b939
2 changed files with 17 additions and 14 deletions
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18
src/timer.rs
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@@ -1,11 +1,13 @@
use arduino_hal::{clock::Clock, pac::TC0, DefaultClock};
// Raises two interrupts: TIMER0_COMPA every period cycles/1024
// and TIMER0_COMPB compb_cocunt cycles/1024 after TIMER0_COMPA
pub fn segment_timer_init(tc0: TC0, seg_freq: u32, on_div: u32) {
// 16_000_000 / 1024 / 100 => 156 (100Hz|10ms)
let ocra = DefaultClock::FREQ / 1024 / seg_freq;
let ocrb: u32 = ocra / on_div;
// Sets up timer to rise two interrupts:
// 1. TIMER0_COMPA - every segment_rate_us μs
// 2. TIMER0_COMPB - segment_on_us μs after TIMER0_COMPA
pub fn segment_timer_init(tc0: TC0, segment_rate_us: u32, segment_on_us: u32) {
// 16_000_000 / 64 * 1000 / 1_000_000 => 250
let ocra = DefaultClock::FREQ / 64 * segment_rate_us / 1_000_000;
let ocrb = DefaultClock::FREQ / 64 * segment_on_us / 1_000_000;
assert!(ocra > ocrb);
// Use CTC mode: reset counter when matches compare value
tc0.tccr0a.write(|w| w.wgm0().ctc());
@@ -16,8 +18,8 @@ pub fn segment_timer_init(tc0: TC0, seg_freq: u32, on_div: u32) {
tc0.ocr0b
.write(|w| w.bits(ocrb.try_into().expect("timer init on_div out of rage")));
// Slow down the timer (CLK / prescale)
tc0.tccr0b.write(|w| w.cs0().prescale_1024());
// Raise interrupt on counter TOP (reset)
tc0.tccr0b.write(|w| w.cs0().prescale_64());
// Raise interrupt on TOP (reset)
// Raise interrupt on B match
tc0.timsk0
.write(|w| w.ocie0a().set_bit().ocie0b().set_bit());